Without limiting the scope of the invention, the background is described in connection with known UART devices, an example of which is the TL16C550 integrated circuit available from Texas Instruments. Many other known UART devices are commonly commercially available.
In transferring data between UART devices, typically each UART is coupled to a modem circuit, and each UART is controlled by a local processor or microprocessor. The UART is an asynchronous transmit and receive device that is used to couple a local data bus to a remote data bus via an asynchronous serial interface. The UART has a parallel data port and control lines for coupling to the local processor, which transfers data to and from the UART on a parallel data bus. Each UART is controlled by the associated local processor through the reading and writing of addressable register locations within the UART. Each UART has an asynchronous serial data port which is typically coupled to a modem. In operation, the UART handshakes data transfers from storage registers within the UART and across the asynchronous interface by using control lines and status inputs coupled to the modem. The data is converted to serial form and shipped across the asynchronous interface in serial form. The modems are linked via a telephone line or local cabling.
FIG. 1 depicts a pair of typical known UART devices coupled for data transfers. For clarity, no modem devices are shown, however the UART circuits include additional output control signals to permit coupling and control through modem devices. In FIG. 1, UART comprises a receive data FIFO 131, a transmit data FIFO 133, a modem status register 139, a parallel-in/serial-out register 141, a serial-in/parallel-out register 135, and a modem control register 137. Interface bus 143 permits a processor, not shown in the figure, to control and communicate with UART 1 through reading and writing operations to addressable bits and registers using the DATA, RD,WR and CS lines conventionally. When the UART requires attention from the processor coupled to bus 143, it will assert the interrupt output, labeled INT.
The asynchronous interface signals of UART 1 are SIN, RTS, CTS, DTR, DCD, RI, DSR and SOUT in FIG. 1. The SIN signal is the serial data input from the other device, here UART 3. The SOUT signal is the serial data output signal from UART 1 and is coupled to the SIN signal of UART 3. The remaining signals can be connected in a variety of ways. The actual connection is dictated by the application and the software and hardware used in the application.
In FIG. 1, RTS (Request to Send) is an output signal that indicates a device is ready to receive data. CTS (Clear to Send ) is an input signal that is checked to see if a remote device is ready for data. DTR (Data Terminal Ready) is an output that indicates to an external device the UART is ready to establish communication.
Typical input signals are also shown in FIG. 1. DCD (Data Carrier Detect) is an input which feeds a bit in the modem status register of the UART devices. RI (Ring Indicator) is another input that feeds a bit in the modem status register. DSR (Data Set Ready) is an input which feeds another bit in the modem status register. These inputs can be enabled to generate an interrupt on the INT output to alert the processor coupled to the processor interface that the UART requires attention. These are hooked up as best suits the software and hardware used in a particular application environment.
UART 3 in FIG. 1 is the same as UART 1, and comprises equivalent elements: a receive data FIFO 331, a transmit data FIFO 333, a modem status register 339, a parallel-in/serial-out register 341, a serial-in/parallel-out register 335, and a modem control register 337. Interface bus 343 allows a second processor to control UART 3 by reading and writing addressable bits and registers in UART 3, again using the CS, WR, RD and DATA lines conventionally.
For clarification, a simple data transfer between UART 1 and UART 3 in FIG. 1 is described. Assume a transfer from a device or processor coupled to UART 1 to a device or processor coupled to UART 3 begins. Since UART 1 is the transmitting UART, a processor coupled to interface bus 143 must first write data words for transmission to the transmit data FIFO 133 of UART 1. Typically software routines running in the transmitting processor check the status of the interface by reading the modem status register 139 using the RD, CS and DATA lines before the transfer begins. The software evaluates the various bits in the modem status register to see if a new transfer is possible. If the status register 139 indicates the remote UART 3 is ready to receive data, the data to be transferred is written to the transmit data FIFO 133. When the transmitting device writes a word to the transmit data FIFO 133 of UART 1, the transmission will begin, and the first word will be output in serial fashion on the SOUT line of UART 1. The data words are then each transmitted by retrieving them from the transmit data FIFO 133 and placing each word into the parallel-in/serial-out register 141. The register 141 then shifts and transmits the bits serially on the SOUT output of UART 1.
The data transmitted from the SOUT output of UART 1 is received at the SIN input of UART 3. UART 3 will then shift the serial bits into its serial-in/parallel-out register 335 and as each word is completely shifted in, the words are placed in parallel fashion into locations in the receive data FIFO 331 of UART 3. If UART 3 fills its receive data FIFO 331 with data words which are shifted in through the SIN input of UART 3 and into the serial-input/parallel-output register 335, UART 3 will assert an interrupt on the INT output. However, the transmission of data will continue until the transmit data FIFO of the UART 1 is empty, i.e., no interruption in the transmit routine occurs even though the receiving UART 3 may be overwriting data into the receive data FIFO of UART 3. The prior art UART's require that the processors handle all synchronization for the transfer. Also, if the transmission of data continues after the receive data FIFO 331 has filled in the receiving UART, the receiving UART 3 will set an overrun error bit in its modem status register 339.
The user may configure the receiving FIFO with a threshold level that is lower than the size of the FIFO. In the prior art, the receiver may have a threshold of four, for example. By using a threshold level smaller than the available FIFO, it may be possible to avoid an overrun error if the processor coupled to the receiving UART can service an interrupt and read the receive data FIFO before the transmit data FIFO fills it. By setting the trigger level low, the interrupt to the processor occurs earlier and a modem status input to the transmitting UART 1 will be deasserted earlier. However, because the transmitting UART does not respond to the deassertion of a modem status input until the transmit data FIFO is completely empty, the overrun error may still occur with a low threshold.
Although the retransmit data method of overrun error correction was acceptable to the systems of the prior art, as processor throughput rates increase, and data word widths increase there is a need for a UART that will transfer data as efficiently as possible, without the necessity to retransmit large blocks of words to correct an overrun error, and for this to occur with a minimum amount of processor intervention.